1. Field of the Invention
This invention relates to an integrated circuits and, more particularly, to the same using a high frequency clock signal for high speed operations.
2. Description of Related Art
FIG. 1 is a schematic diagram showing a clock distribution system of the microprocessor described in Masuda et al. "The TRON specified microprocessor TX1 for built-in control" ("NIKKEI ELECTRONICS" Sep. 5, 1988).
In FIG. 1, numeral 301 denotes a trunk buffer, 302, a branch buffer, 303, a leaf buffer and 304, a flip-flop respectively.
The clock distribution system shown in FIG. 1 employs a tree structure with three hierarchies. Concretely, an external clock is first inputted to the trunk buffer 301 and the output of the trunk buffer 301 is inputted to the branch buffers 302, thus the clock is relayed and further the outputs of the branch buffers 302 are inputted to the leaf buffers 303, the output of which drive loads, that is, the flip-flops 304.
In the circuit configuration of FIG. 1, in order to minimize differences in gate delay times among the buffers, numbers of the leaf buffers driven by the respective branch buffers, numbers of the flip-flops driven by the respective leaf buffers and wiring load capacities are equalized.
As a degree of integration of the recent integrated circuits becomes high, the wiring of the integrated circuit is elongated and the fan out (load connected to a gate output) is increased, thus the load driven by the clock driver is becoming heavy. Further, owing to the high speed operation of the integrated circuit, a clock frequency which the clock driver is to output is becoming high.
Thus, when an internal clock having a heavy load is driven at a high speed, switching noise arises due to a large switching current and this noise has a bad effect on other circuits.
Further, as the clock frequency becomes high, clock skew on a chip due to delay for wiring can not be neglected and it becomes hard to feed the internal clock having the same phase to each part of the chip.
In addition, as the clock frequency becomes high, the power consumption per unit time increases due to the passing current generated in the clock driver. This requires a large size transistor as the clock driver to drive the heavy load, thus causing an important problem.
In the above conventional configuration of FIG. 1, the clock distribution system employs the three hierarchies tree structure to reduce the load driven by the respective drivers. In addition, the load capacity driven by each buffer in the same hierarchy is equalized to reduce the clock skew.
However, in the example of FIG. 1, because of increase in a number of driver stages delay of the internal clock to the external clock becomes large. Further it is required to adjust the load capacity driven by each driver to avoid generation of the skew among the output signal of each driver. To this end, in the case of employing the clock distribution system of FIG. 1, the circuit design becomes complicated and burdens the engineers with a heavy load of the designing.
In view of the above problem, the inventions of Japanese Patent Application Laid-Open No. 60-257543 (1985) and Japanese Patent Application Laid-Open No. 1-112808 (1989), for example, have been proposed.
The invention of Japanese Patent Application Laid-Open No. 60-257543 (1985) is "characterized by comprising a wave shaping circuit for shaping a synchronous signal wave, a plurality of functional circuit portions each operation of which is controlled in synchronization with the output of the wave shaping circuit, a looped first wiring which surrounds a plurality of said functional circuit portions and is fed the output of said wave shaping circuit, a plurality of second wirings each of which takes out the synchronous signal at any point of said first wiring and supply it to each of a plurality of said functional circuit portions".
The invention of Japanese Patent Application Laid-Open No. 60-257543 (1985) will be concretely explained referring to FIG. 2 showing a block diagram of an IC chip.
In FIG. 2, an outermost frame shows one IC chip, one peripheral side of which is provided with a clock driver 311. The clock driver 311 shapes the wave form of a clock signal .phi. for synchronization supplied from the exterior of the IC chip. The shaped clock signal .phi. is fed to a looped wiring 330.
The interior of the IC chip is provided with a memory circuit 312 such as a ROM or RAM which is controlled in synchronization with the clock signal .phi., a logic portion 313 for controlling the memory circuit 312 and other logic portions 314 through 319.
The looped wiring 330 is configured of a looped wiring portion 330A surrounding the abovementioned memory circuit 312 and logic portion 313, a looped wiring portion 330B surrounding the logic portions 314 and 315, a looped wiring portion 330C surrounding the logic portion 316, and a looped wiring portion 330D surrounding the logic portions 317 and 318. Each of the looped wiring portions 330A through 330D and each of the logic portions 313 through 319 are connected by the second wirings 331 through 344, respectively.
In the above invention of Japanese Patent Application Laid-Open No. 60-257543 (1985), the clock signal is fed to each of the logic portions 313 through 319 with the looped wiring 330, thus the phase difference of the clock signals does not become large. Therefore, it is possible to somewhat control generation of the clock skew, but with only provision of the looped wiring 330, it can not cope with other problems.
Further, the invention of Japanese Patent Application Laid-Open No. 1-112808 (1989) discloses "an integrated circuit having an external clock input terminal, a plurality of driver circuits for internal clock signal lines for supplying an inputted clock from the external clock input terminal to the internal clock signal lines, and a plurality of wirings for connecting between said external clock input terminal and a plurality of said driver circuits for the internal clock signal lines, wherein a plurality of the wirings have substantially the respective same wiring impedances".
The invention of Japanese Patent Application Laid-Open No. 1-112808 (1989) will be explained referring to FIG. 3 showing an integrated circuit configuration of the invention.
In FIG. 3, numeral 401 through 403 denote driver circuits, 404, an input buffer, 405, an external clock input terminal, 406, a capacitor, 408, a clock signal line, and 412 through 414, wirings.
The clock inputted from the external clock input terminal 405 is supplied to the driver circuit 403 disposed near the external clock input terminal 405 through the input buffer 404 and the wiring 414.
The clock inputted to the input terminal 405 is supplied to the driver circuit 401 through the input buffer 404 and the wiring 412, simultaneously supplied to the driver circuit 402 through the input buffer 404 and the wiring 413. The clock is supplied to the clock signal line 408 by the driver circuits 401, 402 and 403. The wiring 414 is connected with the capacitor 406.
In such the invention as Japanese Patent Application Laid-Open No. 1-112808 (1989), the wiring impedances of the respective wirings 412, 413 and 414 from the input buffer 404 to the respective driver circuits 401, 402 and 403 are substantially equalized by suitably setting the capacitor 406 capacitance. Therefore, the clocks' attenuations and phase shifts in the wiring 412, 413 and 414 are equalized.
However, it is considered that in the invention of Japanese Patent Application Laid-Open No. 1-112808 (1989), the clock's phase difference arises in many logic circuits connected from the clock signal wire line 408 to further distances, thus the above invention can not give the solutions of the present problems.